Currently, multi-core architectures are used to address the demand for higher computing throughput. Typically, a multi-core processor includes two or more independent processing units (“cores”) that read and execute program instructions. Typically, the cores are integrated onto an integrated circuit die, or onto multiple dies in a single chip package.
The cores and other components on a chip are interconnected using a communication network, e.g., an on-chip interconnect. Typically, the on-chip interconnect includes wire conductors and other transmission media to communicate data among processing and storage units on the chip. The dramatic rise in the number of the cores on a single chip has resulted in the growing complexity of the interconnect fabric.
Generally, a mesh interconnect fabric refers to a network topology in which each node (station) of the mesh relays data for the network. All mesh nodes cooperate in the distribution of data in the network. A mesh network whose nodes are all connected to each-other is a fully connected network. Fully connected networks have the advantages of security and reliability. However, in such networks, the number of connections, and therefore the cost, goes up rapidly as the number of nodes increases.
Currently, high bandwidth mesh interconnects consume a lot of power and chip area that increases the manufacturing cost.